1. Field of the Invention
The present invention relates to a display apparatus, and more particularly relates to a display apparatus with a data line driving circuit, and a data line driving method.
2. Description of Related Art
A time division drive, in which a plurality of data lines are sequentially selected and consequently display signals are written into pixels, is one of techniques that are widely used for a display apparatus. A merit of the time division drive is to make it possible to reduce the number of the buffers provided in a driver IC. The display apparatus that employs the time division drive can drive the pixels by using the buffers whose number is smaller than the number of the data lines on a panel. This is effective for decreasing the electric power consumption and chip area of the driver IC.
The display apparatus of an active matrix type uses a TFT (Thin Film Transistor) as a time divisional switching element on a panel substrate in many cases. The TFT is classified into two types of an amorphous TFT and a polycrystalline TFT. The polycrystalline TFT is known to be higher in mobility than the amorphous TFT. For this reason, since the size of the time divisional switch mounted on the panel substrate can be made small, the time division drive is applied to the display apparatus, which uses the polycrystalline TFT in many cases.
A conventional technique in which a time divisional switch and a shift register are provided on a panel substrate and a time division drive is performed is described in Japanese Laid Open Patent Application (JP-A-Heisei 11-327518: first conventional example). Also, a conventional technique in which a capacitance coupling between data lines adjacent to each other is reduced to suppress the display unevenness such as ghost and longitudinal stripe is described in Japanese Laid Open Patent Applications (JP-P2000-267616A and JP-P2003-337320A: second and third conventional examples). The second conventional example describes the technique to control such that a part of the ON periods of time divisional switches connected to data lines adjacent to each other is overlapped to reduce the capacitance coupling between the data lines adjacent to each other. The third conventional example describes the technique in which an impedance wiring, which is lower in resistance than a data line, is connected to the capacitance coupling between the data lines adjacent to each other, to reduce the capacitance coupling between the data lines.
Moreover, two sets of time divisional switch groups are provided to which the display signals of different systems are supplied. ON periods of the time divisional switch groups adjacent to each other are controlled so as not to overlap with each other, in each of the two sets of the time divisional switch groups, and the display unevenness is consequently controlled, in Japanese Laid Open Patent Application (JP-P2004-309822A: fourth conventional example).
When the driver IC in which the time divisional switches are provided is mounted on the panel substrate, the long side of the driver IC is shorter than a corresponding side of a pixel region in which the pixels are arranged. Therefore, it is required to provide wirings between the output terminal of the driver IC and the pixel region. At this time, in order to avoid use of a large size glass substrate because of the wirings, a pitch between the respective wirings is designed to be as narrow as possible. Thus, a coupling capacitance value between the wirings becomes large. Thus, in the driver IC in which the time divisional switch is used to perform the time division drive on the amorphous TFT, the coupling capacitance value between the wirings influences a signal on the adjacent data line to indicate an undesirable signal value and brings about a display unevenness. The generating mechanism of the display unevenness caused by the data line drive according to the conventional technique will be described below with reference to FIG. 1 and FIGS. 2A to 2I.
FIG. 1 is a circuit diagram showing the configuration of time divisional switches mounted on the data line driving circuit according to a conventional example. FIGS. 2A to 2I are timing charts showing a data line driving operation that is performed in the circuit diagram shown in FIG. 1.
With reference to FIG. 1, the data line driving circuit according to the conventional technique includes buffers 71-1 to 71-4 for driving a plurality of data lines, and time divisional switches 81, 82 and 83 provided between output terminals 72-1 to 72-4 of the buffers 71-1 to 71-4 and each of the plurality of data lines. In detail, the data line driving circuit according to the conventional technique includes the buffer 71-1 for driving data lines R1, G1 and B1 and the time divisional switches 81, 82 and 83 provided between the output terminal 72-1 of the buffer 71-1 and each of the data lines R1, G1 and B1. The time divisional switches 81, 82 and 83 are turned on or off in response to control signals 91, 92 and 93, and control the electric connection or disconnection between the output terminal 72-1 and the data lines R1, G1 and B1, respectively. Similarly, the other buffers 71-2 to 71-4 are electrically connected to or disconnected from R2 to R4, G2 to G4 and B2 to B4 through the time divisional switches 81, 82 and 83, respectively.
With reference to FIGS. 2A to 2I, before a time T1, a scanning signal is supplied to a scanning line Yn, and TFTs connected to the scanning line Yn are turned on. At the time T1, when the time divisional switch 81 is turned on, the buffers 71-1, 71-2, 71-3 and 71-4 drive the data lines R1, R2, R3 and R4, respectively. Subsequently, at a time T2, the time divisional switch 81 is turned off. Thus, the data lines R1, R2, R3 and R4, since they being electrically disconnected from the buffers 71-1, 71-2, 71-3 and 71-4, become in high impedance states and hold display signals corresponding to a display data. Also, at the time T2, the time divisional switch 82 is turned on, and the buffers 71-1, 71-2, 71-3 and 71-4 drive data lines G1, G2, G3 and G4, respectively. At this time, the data lines R1, R2, R3 and R4, which are adjacent to the data lines G1, G2, G3 and G4, respectively, are in the high impedance states. Therefore, when the data lines G1, G2, G3 and G4 are driven, the display signals (the voltage values) held in the data lines R1, R2, R3 and R4 are varied by the coupling capacitances.
Next, at a time T3, the time divisional switch 82 is turned off. Thus, the data lines G1, G2, G3 and G4, since they are electrically disconnected from the buffers 71-1, 71-2, 71-3 and 71-4, become in the high impedance states and hold the display signals corresponding to the display data. Also, at the time T3, when the time divisional switch 83 is turned on, the buffers 71-1, 71-2, 71-3 and 71-4 drive data lines B1, B2, B3 and B4. At this time, the data lines G1, G2, G3 and G4, which are adjacent to the data lines B1, B2, B3 and B4, respectively, and the data lines R2, R3 and R4 are in the high impedance states. Therefore, when the data lines B1, B2, B3 and B4 are driven, the display signals (the voltage values) held in the data lines G1, G2, G3 and G4 and the data lines R2, R3 and R4 are varied due to the coupling capacitances.
Next, at a time T4, the time divisional switch 83 is turned off. Thus, the data lines B1, B2, B3 and B4, since they are electrically disconnected from the buffers 71-1, 71-2, 71-3 and 71-4, become in the high impedance states and hold the display signals corresponding to the display data. After the time T4, the TFTs connected to the scanning line are turned off, and the signal (the voltage value) on each data line at the time T4 is written to each pixel.
As mentioned above, the voltages held in the data lines R1, G1, G2, G3 and G4 are varied by ΔV1 by driving the data lines adjacent to any one of the right and left side only one time, and the voltages held in the data lines R2, R3 and R4 are varied by ΔV1+ΔV2 by driving the data lines adjacent to the right and left sides two times. Here, when a coupling capacitance value between the data lines is assumed to be Cc, a parasitic capacitance value of each data line is assumed to be Cd, and a voltage written to the adjacent data line at a next time is assumed to be ΔVsig, a voltage variation amount ΔV caused by the coupling capacitance value resulting from the adjacent data line is the capacitance voltage variation amount ΔV=ΔVsig·Cc/(Cd+Cc).
In this way, the voltage variation amount ΔV (ΔV1, ΔV2) is also varied on the basis of the display signals sent to the adjacent data lines. Theoretically, the voltage variation amount ΔV can be reduced by decreasing a coupling capacitance value Cc, increasing a parasitic capacitance Cd or decreasing ΔVsig. However, the increase in the parasitic capacitance Cd is not preferred because not only the electric power consumption is increased, but also the lack of the write current to the pixel is caused. Also, the reduction of the coupling capacitance Cc can be attained by widening an interval between the wirings. However, the wiring region is made larger, and the panel size is made greater.
According to the second conventional example, time divisional switches are controlled based on sampling pulses which are generated by a shift register and sequentially shifted. According to this circuit configuration, one buffer drives the several tens or more data lines. Thus, since the wiring length of the display signal line becomes long, the parasitic capacitance is made larger, which increases the electric power consumption. Also, in the data line away from the buffer, the waveform is made dull, which brings about the lack of the write current, and the contrast is reduced. Moreover, the continuous data lines are controlled by the sampling signal generated by the shift register. Thus, in case where gamma compensation is independently performed for each of R, G and B, a gray scale voltage generating circuit is required to be provided inside the driver IC. Thus, the chip area is made larger.